In many applications, including digital communications, clock and data recovery (CDR) must be performed before data can be decoded. Generally, in a digital clock recovery system, a reference clock signal of a given frequency is generated together with a number of different clock signals having the same frequency but with different phases. In one typical implementation, the different clock signals are generated by applying the reference clock signal to a delay network. Thereafter, one or more of the clock signals are compared to the phase and frequency of an incoming data stream and one or more of the clock signals are selected for data recovery.
A number of existing digital CDR circuits use one or more analog phase interpolators to generate a clock signal of a desired phase between the phase of two input signals. It has been found that most analog phase interpolators demonstrate a non-linear phase output in response to a control input. This, in turn, adversely affects the performance of the CDR circuit. The interpolator non-linearity is often attributed to variations in process, voltage, temperature or aging (PVTA).
A need therefore exists for improved techniques for interpolating two input clock signals to generate a clock signal having a phase between the phase of the two input clock signals. A further need exists for improved techniques for linearizing the phase output of an analog interpolator in response to a control input.